1. Field of the Invention
The present invention relates to a circuit for the input and output of data in a semiconductor memory as well as a method therefor. More particularly, this invention relates to a circuit and method for the transfer of data in a synchronous semiconductor memory which is capable of generating a plurality of data words during each cycle of a reference clock signal and transmitting the generated data words to the synchronous semiconductor memory.
2. Description of the Related Art
Modern computer systems generally use a synchronous semiconductor memory as a main memory, driven by a system or reference clock signal, in order to increase an operation rate of the memory. Furthermore, the synchronous semiconductor memory of the modern computer system typically employs a double data rate (DDR) method for transmitting and receiving data, which uses both a rising and a falling edge of one reference clock signal to further increase a processing rate of memory data.
By using the DDR method, two or more data words may be processed during one reference clock cycle tCC. In accordance with the modern computer system design, the synchronous semiconductor memory processes various internal data in synchronism with the reference clock. This is important not only in order to increase an operating margin of the semicondutor memory but also to increase the speed at which memory data is processed.
Utilizing the DDR method, one half of the reference clock cycle tCC (i.e., tCC/2), is a bit time of each data word which is being externally transmitted. The semiconductor memory generally includes two lines having the bit time of tCC, in which the data on one line is processed according to the rising edge of the reference clock signal CLK and the data on the other line is processed according to the falling edge of the reference clock signal CLK.
FIG. 1 is a schematic showing a data transfer circuit for a synchronous semiconductor memory according to the prior art. According to this conventional circuit design, data is transferred to and from the memory according to data paths. For example, a data path in a read mode employs a multiplexer 101 and a driver 103. The multiplexer 101 selects between the two internal data lines according to reference clock signals CLK and /CLK. The driver 103 is, in turn, driven by a signal output from the multiplexer 101 and thereby produces a corresponding output signal.
A data path in a write mode employs two data receivers 105 and 107. The data receivers 105 and 107 each receive an external data input signal corresponding to the output signal from the driver 103, and are activated according to the reference clock signals CLK and/CLK, respectively. Within the memory, particularly within DRAM-type memory, a circuit design which minimizes operation current of the data receivers is extremely important.
FIG. 2 is a schematic illustrating one example of a data receiver 105 or 107, as seen in FIG. 1, according to the prior art. The operation of this conventional data receiver is as follows. When a first control signal SAMPLE, comprising the external data input signal described above, rises to high, path transistors 201 and 203 are turned on. The path transistors 201 and 203 are thus activated, and a charge received from a reference terminal REFERENCE VOLTAGE and a pad PAD through the path transistors 201 and 203 is stored in terminals 205 and 207, respectively. When the first control signal SAMPLE then falls to low, the path transistors 201 and 203 are turned off, and a pull-up transistor 211 of a latch 209 is simultaneously turned on. When a second control signal SENSE then rises to high, a pull-down transistor 213 of the latch 209 is turned on, thereby amplifying the charge stored in the terminals 205 and 207. The amplified data is then received by another memory circuit (not shown).
Power consumption is a tremendous concern in a semiconductor memory.
Unfortunately, the data receivers depicted in FIGS. 1 and 2 consume a certain amount of power when in use. Furthermore, according to the conventional art, one data receiver is required for each data word being processed during one reference clock cycle. Accordingly, as the number of processed data words per clock cycle increases, the number of data receivers needed increases, and power consumption increases. The industry is therefore in need of an efficient circuit and method for transferring data to and from a semiconductor memory which is capable of processing multiple data words during a single clock cycle with reduced power consumption.